# Lower phase — slice 1 (relations, booleans, short-circuit)

Branch `ast-stage-c`.  Suite **181/181**; self-hosting fixpoint **OK**
(**3,104,868 bytes**; L0 was 3,090,949).  Plan: `docs/plan-lower.md`.

## What landed

`Lower` now covers, in addition to L0:

- **Relations** `=` `#` `<` `<=` `>` `>=` on scalar operands →
  `QbeGen.Cmp(op, …)` (`AST.Op*` mapped to `SymTab.Op*`), result
  `BOOLEAN`.
- **`NOT`** / `~` → `QbeGen.NotQ`.
- **Short-circuit `AND`** (`Term`) and **`OR`** (`SimExpr`): the walk
  brackets the RHS with `DelayBegin`/`DelayEnd`, then emits the same
  merge block (`Slot4`, `NewLabel` ×3, `Jnz`, `EmitLabel`, `DelayFlush`,
  `StoreW`, `Jmp`, `LoadW`, `CopyOp`) as the grammar — so the temp/label
  counters line up and the image is byte-identical.
- **`TRUE`/`FALSE`** constants in `LowerDesign`.
- `CanLower` accepts scalar classes `INT/BOOLEAN/CHAR/UCHAR/ENUM`.

## Verified

`gen_ssa/TLower1L.ssa` (a program with `(x<y) AND (y>0)` and
`NOT (x=y) OR (x<=y)`) is **byte-identical** to the legacy image
(`lower_ok t_lower1.mod`).

## Next

L2: control flow (`IF`/`WHILE`/`REPEAT`/`LOOP`/`FOR`/`RETURN`/`HALT`) —
statements, so `CanBody` grows and `LowerUnit` walks statement nodes.