M2compiler-V3/docs/session-2026-09-27.md

Session save — 2026-09-27: short-circuit AND/OR

master — suite 111/111, tree clean except the user's uncommitted compiler/toto.mod edit.

Done today

Short-circuit AND/OR (task 1). Tag v3-short-circuit; details in docs/summary_short-circuit.md.

• V3 used to evaluate both sides; gm2 and the compiler's own sources rely on short-circuit (~25 guard sites like … AND (tform[t] = FAlias)).
• Implemented by deferring the RHS operand's code: QbeGen.DelayBegin buffers it, DelayEnd restores output, DelayFlush replays it inside the branch; a 4-byte memory slot (Slot4/StoreW/LoadW) merges the branch results (robust when the RHS spans blocks; a phi was not).
• SimExpr (OR) / Term (AND): if a { r=1/0 } else { <RHS>; r=b }.
• The wip/short-circuit branch (14 failing tests) was debugged — two bugs: DelayFlush popped the wrong index, and the CopyOp-only merge collapsed the branches to one operand — then merged and the branch deleted.

In progress (task 2: full self-image)

The self-compiled V3 (/tmp/M2self) compiles a single file to a byte-identical .ssa, but the whole compiler source set still aborts (rc 134), now in the scanner's GetName (LexName ← GetIdent ← ProcTypeSection) — a bounds trap in the token-text copy loop (0 ≤ i ≤ count on the destination buffer). Likely the caller's buffer descriptor header is wrong; needs more diagnosis. (Earlier self-image aborts fixed: Resolve's eager-AND tform[t] guard → resolved by short-circuit.)

Next

1. Diagnose the GetName bounds trap; iterate until /tmp/M2self compiles the whole set to a byte-identical M2.ssa (full fixpoint).
2. Cross-stage FileIO selection and bootstrap/fixpoint.sh (Stage1 gm2 → Stage2 V3 → Stage3 V3), with the stage-aware CR flag (-m for gm2, no -m for V3).

Tags added

v3-short-circuit (merge + summary).